1. Field of the Invention
Example embodiments of the disclosed methods and systems relate to an etching solution for silicon oxide and methods of manufacturing a semiconductor device using the etching solution. More particularly, example embodiments of the disclosed methods and systems relate to an etching solution for silicon oxide employed in etching processes to expand an opening formed on a silicon oxide layer, as well as methods of manufacturing a semiconductor device using the etching solution.
This application claims priority under 35 USC § 119 to Korean Patent Application No. 2005-101017 filed on Oct. 26, 2005, the contents of which are herein incorporated by reference in their entirety.
2. Description of the Related Art
As semiconductor devices have been required to process data at ever faster speeds, the sizes of semiconductor elements have been considerably reduced, which in part have spurred the development of three-dimensional, multi-layer structures. When wiring (and/or other patterns) in a semiconductor device are highly integrated, an interval between the wirings (or other patterns) is greatly reduced. Unfortunately, this may lead to an increased problem with respect to alignment errors that occur during the photographic processes for making photoresist patterns used in etching/forming contact holes through insulating interlayer between wirings and/or other patterns.
Because current semiconductor devices have design rules below about 80 nm, an opening formed through an insulating interlayer between conductive structures, such as bit lines, may have a greatly reduced width. As the width of the opening exposing a contact region or a pad formed on a substrate is considerably decreased, the exposed area of the contact region (or pad) also may be considerably reduced. As a result, because of an insufficient contact margin between a plug for a capacitor and another contact region (or pad), the plug for the capacitor may not make the appropriate contact.
To address the above-mentioned problem, an etching solution including hydrogen fluoride and ammonium fluoride (e.g., an LAL solution) is used to enlarge a width of an opening where a plug for a capacitor is formed, thereby ensuring an appropriate contact margin between the plug for a capacitor and another contact region/pad.
Unfortunately, such an etching solution may undesirably etch metal silicide patterns of a conductive structure exposed by the enlarged opening.
FIG. 1 is an electron microscopic picture showing damage to a metal silicide pattern caused by the etching solution including hydrogen fluoride and ammonium fluoride in a process for enlarging an opening formed through a silicon oxide layer. As shown in FIG. 1, the metal silicide pattern may be excessively damaged because the LAL etching solution can easily etch the metal silicide pattern as well as silicon oxide. When the metal silicide pattern is damaged, nitride may penetrate into a damaged portion of the metal silicide pattern during a process for forming a spacer on a sidewall of the metal silicide pattern, thereby increasing the resistance of the metal silicide pattern. As a result, a conductive structure including the metal silicide pattern such as a bit line may have a greatly increased resistance so that electrical characteristics of a semiconductor device may be deteriorated.